TOC Draft for Information Only
ContentSolid-State Drive
Solid-State DriveA solid-state drive, SSD, solid-state device, solid-state disk, is a solid-state storage device that uses integrated circuit assemblies to store data persistently, typically using flash memory, and functioning as secondary storage in the hierarchy of computer storage.Form FactorsStandard HDD form factorsStandard card form factorsDisk-on-a-module form factorsBox form factorsBare-board form factorsBall grid array form factorsStorage InterfaceFlash memoryDRAM3D XPointHost interfaceThe host interface is physically a connector with the signalling managed by the SSD's controller. It is most often one of the interfaces found in HDDs. They include:
Common Host Interfaces
Host InterfaceSATAmSATAPCIeM.2M.2U.2SATA Express
Transfer InterfaceSATASATAPCIeSATAPCIe
SATA 3.0 Transfer Rate6Gb/s6Gb/sN/A6Gb/sN/A
PCIe 3x2 Transfer RateN/AN/A1.969GB/sN/A1.969GB/s
PCIe 3x4 Transfer RateN/AN/A3.938GB/sN/A3.938GB/s
PCIe 3x8 Transfer RateN/AN/A7.877GB/sN/A7.877GB/s
PCIe 4x4 Transfer RateN/AN/A7.877GB/sN/A7.877GB/s
Communications interfaceSince SATA hard drive is the most common data storage before the introduction of solid state drive, the communications interface, AHCI (Advanced Host Controller Interface) protocol, used by SATA hard drive is also adopted by SSD in order to hosted by a SATA host interface. As ACHI protocol was designed for high latency rotating media, a new NVMe (Non-Volatile Memory Express or NVM Express) protocol was designed as the communications interface for PCIe-based SSDs.Differences between AHCI and NVMeThe advantages of NVMe protocol are
ProtocolNVMeACHI
TechnologyDesigned for SSDs with flash technologyDesigned for Hard Drives with spinning disk technology
Latency2.8µs6.0µs
Uncacheable Register Reads
(Each consumes 2000 CPU cycles)0 per command (Two per command)4 per command 8000 cycles, ~ 2.5 μs (Six per non-queue command; nine per queued command) Multicore SupportYesLimited MSI - X and Interrupt Steering (Ensures one core not IOPs bottleneck)Yes, 2048 MSI-X interruptsA single interrup; no steering Parallelism & Multiple Threads (Ensures one core not IOPs bottleneck)No locking, doorbell register per QueueRequires synchronization lock to issue command Maximum Queue Depth (Ensures one core not IOPs bottleneck)Up to 65535 queues; 65536 commands per queueUp to One command queue; 32 commands per queue Efficiency for 4KB Commands (4KB critical in Client and Enterprise)Command parameters in one 64B fetchCommand parameters require two serialized host DRAM fetches Command cycleCommands utilize low CPU cyclesCommands utilize high CPU cycles Controller CycleCommunicates directly with the system CPUMust communicate with the SATA controller Input/Output Operations Per Secondover 1,000K IOPsup to 100K IOPS Sources and References
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