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PCI Express

Technology: PCI Express

Specification Title Spec Rev Document Type Release Date
PCIe Link Activation ECN Link Activation allows software to temporarily disable Link power management, enabling the avoidance of the architecturally mandated stall for software-initiated L1 Substate exits. 4.x ECN December 12, 2017
PCI Code and ID Assignment Specification, Revision 1.10 1.x Specification November 28, 2017
Add a Second PCIe Lane to Type 1216 SDIO Based LGA Module ECN The M.2 Type 1216 Land Grid Array (LGA) Connectivity module is modified to add a second PCIe lane. Referring to Figure 99 on page 127 1.x ECN November 3, 2017
Additional Voltage Value for PWR_1 Rail V0.3 ECN This proposal adds an additional voltage value to the PWR_1 rail in the PCIe BGA SSD 11.5x13 ECR. Table 3 of section 3.4 in the document “PCIe BGA SSD 11.5x13 ECR”, defines the PWR_1 signal as a 3.3V source. This is changed to now also include a 2.5V rail. 1.x ECN November 3, 2017
_DSM Additions for Runtime Device Power Management This ECN adds two capabilities by way of adding functions to the PCI Firmware Spec defined _DSM definition. 3.x ECN October 26, 2017
OCuLink BP Type ECN (Change Bar) The backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal. 1.x ECN October 6, 2017
OCuLink Wiring Chart ECN (Change Bar) a. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table. 1.x ECN October 6, 2017
OCuLink BP Type ECN (Clean) The backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal.  1.x ECN October 6, 2017
OCuLink Wiring Chart ECN (Clean) a. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table.  1.x ECN October 6, 2017
PCI Express® Base Specification Revision 4.0, Version 1.0 This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 4.x Specification October 5, 2017
PCI Express® Base Specification Revision 4.0, Version 1.0 (Change Bar) This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 4.x Specification October 5, 2017
Native PCIe Enclosure Management ECN Defines mechanisms for simple storage enclosure management for NVMe SSDs, consistent with established capabilities in the storage ecosystem, with the first version of this capability defining a register interface for LED control. This ECN defines a new PCI Express extended capability called Native PCIe Enclosure Management (NPEM). 3.x ECN August 18, 2017
Expansion ROM Validation ECN Provide an optional mechanism to indicate to software the results of a hardware validation of Expansion ROM contents. 3.x ECN August 9, 2017
OCuLink CPRSNT# Notice ECN The cable presence (CPRSNT#) signal was incompletely and inaccurately specified in the original OCuLink 1.0 specification. The definition for the logic levels of this signal contradicted the active low naming convention. The direction has multiple contradictions. 1.x ECN May 31, 2017
PCIe CEM Thermal Reporting ECN This ECN specifies changes to the PCI Local Bus Specification Revision 3.0 and the PCI Express CEM Specification 3.0. Changes to the PCI Local Bus Specification cover a new VPD encoding and a 32-bit field. Changes to the PCI Express CEM Specification cover a series of graphs used to classify air flow impedance and thermal properties under varying conditions as well as the test figure and process to create these graphs for a given adapter add-in card. Adapter add-in card types supported by this include all SINGLE-SLOT and DUAL-SLOT PCIe CEM adapter add-in cards without integrated air movers, including standard height adapter add-in cards as well as low-profile adapter add-in cards). Adapter add-in cards with an integrated air mover were not addressed due to the added complication of their integrated air mover in the overall platform’s potential cooling redundancy. 3.x ECN May 31, 2017
PCI Code and ID Assignment Specification Revision 1.9 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications 1.x Specification May 31, 2017
Hierarchy ID Message ECN Defines a new, optional PCI-SIG Defined Type 1 Vendor Defined Message. This message provides software and/or firmware, running on a Function, additional information to uniquely identify that Function, within a large system or a collection of systems. When a single system contains multiple PCI Express Hierarchies, this message tells a Function which Hierarchy it resides in. This value, in conjunction with the Routing ID number uniquely identifies a Function within that system. In clustered system, this message can include a System Globally Unique Identifier (System GUID) for each system. This value, in conjunction with the Hierarchy ID and Routing ID uniquely identifies a Function within that cluster. 3.x ECN March 17, 2017
Enable PCIe and USB 3.1 Gen1 on M.2 Card Key B ECN M.2 Key B (WWAN) is modified to enable PCIe and USB 3.1 Gen1 signals to be simultaneously present on the connector. This enables support for a single SKU M.2 card that supports both PCIe and USB 3.1 Gen1. There are two implementation options enabled: 1. State #14 in the “Socket 2 Add-in Card Configuration Table” is re-defined to indicate an Add-in Card built to the PCI Express M.2 Specification, Revision 1.1 or later where both PCIe and USB 3.1 Gen1 are both present on the connector. The choice of Port Configuration is vendor defined. This enables the host to unambiguously determine that PCIe and USB 3.1 Gen1 are present on the connector. 2. States #4, 5, 6, 7 in the “Socket 2 Add-in Card Configuration Table” are re-defined to indicate that in addition to USB 3.1 Gen1, PCIe may be present on the connector. This definition was used by M.2 cards built to the PCI Express M.2 Specification, Revision 1.0 (USB 3.1 Gen1 on connector; PCIe is “no connect”). This definition is now also permitted to be used by M.2 cards built to PCI Express M.2 Specification, Revision 1.1 or later to indicate that PCIe and USB 3.1 Gen1 are both present on the connector. This allows GPIO port configurations to remain consistent with all other existing states. 1.x ECN March 17, 2017
Flattening Portal Bridge (FPB) ECN This ECR is intended to address a class of issues with PCI/PCIe architecture that relate to resource allocation inefficiency. To explain this, first we must define some terms: Static use cases, refer to scenarios where resources are allocated at system boot and then typically not changed again Dynamic use cases, refer to scenarios where run-time resource rebalancing (allocation of new resources, freeing of resources no longer needed) is required, due to hot add/remove, or by other needs. In the Static cases there are limits on the size of hierarchies and number of Endpoints due to the Bus & Device Number “waste” caused by the PCI/PCIe architectural definition for Switches, and by the requirement that Downstream Ports associate an entire Bus Number with their Link. This proposal addresses this class of problems by “flattening” the use of Routing IDs so that Switches and Downstream Ports are able to make more efficient use of the available space. 3.x ECN February 15, 2017
PCIe BGA SSD 11.5x13 ECN This proposal adds a new 11.5 mm x 13 mm PCIe BGA SSD form factor to the M.2 v1.1 specification.  1.x ECN February 8, 2017
OCuLink Skew A PCI Express Receiver is required to tolerate 6 ns of lane to lane skew when operating at 8.0 GT/s. The PCI Express OCuLink Specification allowed the cable assembly to consume the entire budget. The Transmitter and traces routing to the OCuLink connector need some of this budget. The PCI Express Card Electromechanical Specification Revision 3.0 assigns 1.6 ns to the total interconnect lane to lane skew budget. 1.x ECN December 20, 2016
PCI Express M.2 Specification Revision 1.1 The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution. 1.x Specification December 15, 2016
PCI Express M.2 Specification Revision 1.1 with Change Bar The M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution. 1.x Specification December 15, 2016
PCI Express® Mini Card Electromechanical Specification Revision 2.1 This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. 2.x Specification December 15, 2016
PCI Express® Mini Card Electromechanical Specification Revision 2.1 with Change Bar This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. 2.x Specification December 15, 2016
OCuLink Memory Map Change This is a modification of the cable assembly memory map defined in OCuLink 1.0, Appendix A. The addresses for the data bytes contained within the external cable assembly's memory will be reorganized. In addition, some data in these fields are modified. 1.x ECN December 15, 2016
OCuLink Server Change Table 6-12 and Table 6-13 in Section 6.9 are modified to reflect connector requirements for server/datacenter segment. In addition, this proposal also reflects a clarification in the Introduction text, Section 1 to include the server/datacenter market segment. 1.x ECN December 15, 2016
Errata for the PCI Express® OCuLink Specification Revision 1.0 1.x Errata November 4, 2016
PCI Code and ID Assignment Specification Revision 1.8 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification September 21, 2016
PCI Code and ID Assignment Specification Revision 1.8 (Change Bar) This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification September 21, 2016
VF Resizable BARs ECN Similar to, and based on, the Resizable BAR and Expanded Resizable BAR ECNs, this optional ECN adds a capability for PFs to be able to resize their VF BARs. This ECN is written with the expectation that the Expanded Resizable BAR ECN will have been released prior to this ECN’s release. This ECN supports all of the BAR sizes defined by both the Resizable BAR and Expanded Resizable BAR ECNs. 3.x ECN August 25, 2016
SR-IOV Table Updates ECN Update SR-IOV specification to reflect current PCI Code and ID Assignment Specification, regarding PCI capabilities and PCI-E extended capabilities. Clarify the requirements for VFs regarding the other Capabilities added by ECNs that should have updated the SR-IOV specification but did not. 3.x ECN July 5, 2016
Extended Message Data for MSI ECN MSI is enhanced to include an Extended Message Data Field for the function generating the interrupt. The MSI Capability Structure is modified to enable the new feature to be enabled/disabled; and a new Extended Message Data Field to be configured. This change only applies to MSI and not MSI-X. 3.x ECN May 20, 2016
Expanded Resizable BARs ECN The Resizable BAR capability currently allows BARs of up to 512 GB (239), which allows address bits <38:0> to be passed into an Endpoint. This proposal extends resizable BARs to up to 263 bits, which supports the entire address space. 3.x ECN May 5, 2016
Errata for the PCI Express® Base Specification Revision 3.1, Single Root I/O Virtualization and Sharing Revision 1.1, Address Translation and Sharing Revision 1.1, and M.2 Specification Revision 1.0 3.x Errata March 18, 2016
M.2 SSIC Eye Limits Definition ECN Definition of electrical eye limits (Eye Height and Eye Width) at the M.2 connector for SSIC host and device transmitter is proposed to be added in the specification. 3.x ECN December 28, 2015
Root Complex Integrated Endpoints and IOV Updates This ECN implements a variety of spec modifications intended to correct inconsistencies related to, and to support more consistent implementation of, Root Complex integrated Endpoints, with a particular focus on issues relating to Single Root IO Virtualization (SR-IOV). 3.x ECN December 11, 2015
PCI Express Base Specification Revision 3.1a with Change Bar This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.  3.x Specification December 7, 2015
PCI Express Base Specification Revision 3.1a This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.  3.x Specification December 7, 2015
Emergency Power Reduction Mechanism with PWRBRK Signal ECN This ECN defines two sets of related changes to support an Emergency Power Reduction mechanism and to provide software visibility for this mechanism: 1. The Card Electromechanical Specification is updated to define an optional Emergency Power Reduction mechanism using RSVD pin B30. 2. The PCI Express Base Specification is updated to define an optional mechanism to indicate support for Emergency Power Reduction and to provide visibility as to the power reduction status of a Device. 3.x ECN December 1, 2015
Supporting PCIe and SATA BGA form factor for SSDs ECN This ECN is intended to define a new form-factor and electrical pinout to the M.2 family. This proposal will allow PCIe and SATA to be delivered using a BGA package, expanding the use of the PCIe and SATA protocols in small form-factor applications. The new BGA pinout content is based on the Socket 3 Key-M definitions. BGA pinout supports additional pins than defined for Socket-3, for soldered-down form-factors. 1.x ECN November 10, 2015
PCI Express® OCuLink Specification Revision 1.0 This document is a companion Specification to the PCI Express Base Specification and other PCI Express® 2 documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation 3 of internal and external small form factor PCI Express® connectors and cables optimized for the client and mobile 4 market segments. This Specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling 5 needs in the PCI Express Base Specification. 6 No assumptions are made regarding the implementation of PCI Express compliant components on either side of 7 the Link; such components are addressed in other PCI Express Specifications. 1.x Specification October 23, 2015
Designated Vendor-Specific Extended Capability ECN Define a Vendor-Specific Extended Capability that is not tied to the Vendor ID of the Component 5 or Function. This capability includes a Vendor ID that determines the interpretation of the remainder of the capability. It is otherwise similar to the existing Vendor-Specific Extended Capability. 3.x ECN August 25, 2015
PCI Code and ID Assignment Specification Revision 1.7 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification August 25, 2015
PCI Code and ID Assignment Specification Revision 1.7 with change bar This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification August 25, 2015
WWAN Key C Definition This ECR describes the necessary changes to enable a new WWAN Key C definition to be included as an addition to the existing spec. The intent is to create a dedicated WWAN socket Key and pinout definition. This new pinout definition will be focused on WWAN specific interfaces and needs.  1.x ECN March 18, 2015
PCI Code and Assignment Specification Revision 1.6 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification December 9, 2014
PCI Code and Assignment Specification Revision 1.6 with Change Bar This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification December 9, 2014
M.2 2242 WWAN Module Add 2242 form factor for WWAN modules using Socket 2 with key B. 1.x ECN November 20, 2014
Errata for the PCI Express Base Specification Revision 3.0 3.x Errata October 23, 2014
Power-up requirements for PCIe side bands in a Vbat powered system In ECN “Power-up requirements for PCIe side bands (PERST#, etc.)” - submitted by Dave Landsman and Ramdas Kachare - section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset. 1.x ECN October 20, 2014
Tx Blanking and SYSCLK on Socket 1 Related Pinouts The proposed change is to include 2 GNSS Aiding signals, that we already have allocated in the Type 1216 pinout, to the Socket 1 Key E pinout and Type 2226/3026 pinout. Due to lack of free pins in the Key E pinout, it is proposed to define 2 SDIO Input signals as dual functional pins. They would be defined with their original SDIO functionality along with and alternate GNSS Aiding signals functionality to enable a GNSS solution on Type 2230 solutions on Socket 1 Key E solutions. The GNSS signals to be added are the Tx Blanking and SYSCLK signals and it is suggested to overlay them on the SDIO RESET# and SDIO CLK respectively which are also inputs. In this way it is less likely to cause a potential contention.  1.x ECN October 19, 2014
M.2 COEX Signal Definition - UART Definition of two of the three COEX pins as a UART Tx/Rx communication path between Socket 1 and Socket 2 in favor of WWAN ßà Connectivity coexistence. The intent is to definitively define the location of the source and sink sides of the signal path.  1.x ECN October 19, 2014
Transition of NFC Signals from 3.3V to 1.8V The proposed change is to change the current voltage level of the NFC related signals (I2C DATA, I2C CLK and ALERT#) on the Connectivity pinouts and definitions from 3.3V to 1.8V signal level to better align with future platforms operating signal levels typical in the industry.  1.x ECN October 19, 2014
Extension Devices Provide specification for Physical Layer protocol aware Retimers for PCI Express 3.0/3.1. 3.x ECN October 6, 2014
Power-up requirements for PCIe side bands (PERST#, etc.) Section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset. 1.x ECN September 18, 2014
M.2 Signal Definition – Audio & ANTCTL Functions Definition of the four Audio pins to provide definitive functions assigned to each pin of the Audio interface. 1.x ECN September 3, 2014
SMBus interface for SSD Socket 2 and Socket 3 SMBus interface signals are included in sections 3.2 and 3.3 and related minor clarifications added to sections 1.2, 1.3, 2.2, 4.1, 4.2, 5.2.2, and 5.3. 1.x ECN August 11, 2014
Add USB 3.0 to the Mini Card Mobile broadband peak data rates continue to increase. With LTE category 5, USB 2.0 will not meet the performance requirements. LTE category 5 peak data rates are 320 Mbps downlink; 75 Mbps uplink. Most USB 2.0 implementations achieve a maximum of about 240 Mbps throughput. Looking longer term, the ITU has set a target of 1 Gbits/s for low mobility applications for IMT Advanced. 2.x ECN August 8, 2014
NOP DLLP This ECN accomplishes two housekeeping tasks associated with DLLP encoding. 3.x ECN June 17, 2014
Separate Refclk Independent SSC Architecture (SRIS) JTOL and SSC Profile Requirements Modifies specifications to provide revised JTOL curve for SRIS mode and provides additional frequency domain constraint of SSC profile jitter on reference clocks. 3.x ECN March 31, 2014
PCI Code and Assignment Specification Revision 1.5 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification March 6, 2014
PCI Code and Assignment Specification Revision 1.5 with Change Bar This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification March 6, 2014
Tighten Mini Card Power Rail Voltage Tolerance Modify the Mini Card specification to tighten the power rail voltage tolerance. 2.x ECN March 3, 2014
PLL Bandwidth Test Limits Modifies the limits used by the PLL bandwidth test to allow guardband for a single PLL test solution to be used at PCI-SIG compliance workshops without impacting pass/fail results for member companies. 3.x ECN January 24, 2014
PCI Express M.2 Specification Revision 1.0 The M.2 form factor is used for Mobile Add-In cards. The M.2 is a natural transition from the Mini Card and Half-Mini Card to a smaller form factor in both size and volume. The M.2 is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution. 1.x Specification November 1, 2013
PCI Code and Assignment Specification Revision 1.4 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification August 30, 2013
PCI Code and Assignment Specification Revision 1.4 with Change Bar This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification August 30, 2013
Readiness Notifications (RN)  Defines mechanisms to reduce the time software needs to wait before issuing a Configuration Request to a PCIe Function or RC-integrated PCI Function following power on, reset, or power state transitions. 3.x ECN August 29, 2013
PCI Express Card Electromechanical Specification Revision 3.0 This specification is a companion for the PCI Express Base Specification, Revision 3.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. Access Test Channel S-Parameters. 3.x Specification July 21, 2013
PCI Express Architecture Platform Init/Config Revision 3.0 This test specification primarily covers tests of PCI Express platform firmware for features critical to PCI Express. This specification does not include the complete set of tests for a PCI Express System. 3.x Specification June 18, 2013
PCI Express Architecture PHY Test Specification Revision 3.0 This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification 3.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. 3.x Specification June 6, 2013
PCI Express Architecture Configuration Space Test Specification Revision 3.0 This document primarily covers PCI Express testing of all defined PCI Express Device Types and RCRBs for the standard Configuration Space mechanisms, registers, and features in Chapter 6 of the PCI Local Bus Specification and Chapter 7 of the PCI Express Base Specification (some additional tested registers are described in other specifications that are referenced in the individual test description). 3.x Specification June 6, 2013
PCI Express® Architecture Link Layer and Transaction Layer Test Specification Revision 3.0 This test specification primarily covers testing of PCI Express Device and Port types for compliance with the link layer and transaction layer requirements of the PCI Express Base Specification. Device and Port types that do not have a link (e.g., Root Complex Integrated Endpoints, Root Complex Event Collectors) are not tested under this test specification. At this point, this test specification does not describe the full set of PCI Express tests for all link layer or transaction layer requirements. 3.x Specification June 6, 2013
L1 PM Substates with CLKREQ, Revision 1.0a  This ECR defines an optional mechanism, that establishes, depending on implementation, one or more substates of the L1 Link state, which allow for dramatically lower idle power, including near complete removal of power for high speed circuits. 3.x ECN May 30, 2013
M-PCIe This ECR defines a new logical layer mapping of PCI Express over the MIPI Alliance M-PHY1 specification. 3.x ECN May 22, 2013
Precision Time Measurement (PTM), Revision 1.0a Defines an optional-normative Precision Time Measurement (PTM) capability. To accomplish this, Precision Time Measurement defines a new protocol of timing measurement/synchronization messages and a new capability structure. 3.x ECN March 31, 2013
Separate Refclk Independent SSC Architecture (SRIS) Provide specifications to enable separate Refclk with Independent Spread Spectrum Clocking (SSC) architecture. 3.x ECN January 10, 2013
Seasim Software Package The PCI Express 3.0 describes a method to simulate 8GT/s channel compliance using a statistical data eye simulator. To help members perform this simulation, a free open source tool called Seasim is provided below. This tool has been tested by members of the Electrical Working Group on multiple channels and has reached version 0.54 which should be useful for members designing 8GT/s systems.   3.x Specification January 1, 2013
Change Root Complex Event Collector Class Code Change the Sub-Class assignment for Root Complex Event Collector from 06h to 07h. 3.x ECN December 13, 2012
Enhanced DPC (eDPC) This optional normative ECN defines enhancements to the Downstream Port Containment (DPC) ECN, an ECN that enabled automatic disabling of the Link below a Downstream Port following an uncorrectable error. The DPC ECN defined functionality for both Switch Downstream Ports and Root Ports. This ECN mostly defines functionality that is specific to Root Ports, functionality referred to as “RP Extensions for DPC”. 3.x ECN November 15, 2012
PCI Express Architecture Configuration Space Test Specification Revision 2.0a This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. 2.x Specification September 17, 2012
PCI Express Architecture Configuration Space Test Specification Revision 2.0a with Change Bar This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. 2.x Specification September 17, 2012
PCI Express Architecture PHY Test Specification Revision 2.0 This document provides test descriptions for PCI Express electrical testing. It is relevant for anyone building add-in cards or system boards to the PCI Express Card Electromechanical Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices.  2.x Specification September 17, 2012
PCI Express Architecture Link Layer Test Specification Revision 2.0 This test specification primarily covers testing of all PCI Express Port types for compliance with the link layer requirements in Chapter 3 of the PCI Express Base Specification. At this point, this specification does not describe the full set of PCI Express tests for all link layer requirements. Going forward, as the testing gets mature, it is expected that more tests may be added as deemed necessary. 2.x Specification September 17, 2012
PCI Code and Assignment Specification Revision 1.3 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification September 4, 2012
PCI Code and Assignment Specification Revision 1.3 with Change Bar This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification September 4, 2012
PCI Express External Cabling Specification Revision 2.0 This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. 2.x Specification June 22, 2012
PCI Express External Cabling Specification Revision 2.0 with Change Bar This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 5.0 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard5 ™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. 2.x Specification June 22, 2012
Combined Antenna Tuning/Coexistence Signal ECR Modify the PCI Express Mini Card specification to define a new interface for tunable antennas. Modify the PCI Express Mini Card specification to enable existing coexistence signals to operate simultaneously with new tuneable antenna control signals. 2.x ECN May 31, 2012
PCI Express Mini Card Electromechanical Specification Revision 2.0 with Change Bar This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. 2.x Specification April 21, 2012
PCI Express Mini Card Electromechanical Specification Revision 2.0 This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. 2.x Specification April 21, 2012
PCI Code and Assignment Specification Revision 1.2 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification March 15, 2012
PCI Code and Assignment Specification Revision 1.2 with Change Bar This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification March 15, 2012
PCI Code and Assignment Specification Revision 1.1 This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification March 15, 2012
PCI Code and Assignment Specification Revision 1.1 with Change Bar This specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. 1.x Specification March 15, 2012
Downstream Port Containment (DPC) This ECN defines a new error containment mechanism for Downstream Ports as well as minor enhancements that improve asynchronous card removal. Downstream Port Containment (DPC) is the automatic disabling of the Link below a Downstream Port following an uncorrectable error. This prevents the potential spread of data corruption (all TLPs subsequent to the error are prevented from propagating either Upstream or Downstream) and enables error recovery if supported by software. 3.x ECN February 9, 2012
Lightweight Notification (LN) Protocol This optional normative ECN defines a simple protocol where a device can register interest in one or more cachelines in host memory, and later be notified via a hardware mechanism when any registered cachelines are updated. 3.x ECN October 6, 2011
8.0 GT/s Receiver Impedance Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. 3.x ECN August 18, 2011
PASID Translation The Process Address Space ID (PASID) ECN to the Base PCI Express Specification defines the PASID TLP Prefix. This companion ECN is optional normative and defines PASID TLP Prefix usage rules for ATS and PRI. 1.x ECN March 31, 2011
Process Address Space ID (PASID) This optional normative ECN defines an End-End TLP Prefix for conveying additional attributes associated with a request. The PASID TLP Prefix is an End-End TLP Prefix as defined in the PCI Express Base Specification. Routing elements that support End-End TLP Prefixes (i.e. have the End-End TLP Prefix Supported bit Set in the Device Capabilities 2 register) can correctly forward TLPs containing a PASID TLP Prefix. 1.x ECN March 31, 2011
Errata for the PCI Express Base Specification Revision 2.1 2.x Errata November 18, 2010
PCI Express Base Specification Revision 3.0 with Change Bar This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 3.x Specification November 10, 2010
PCI Express Base Specification Revision 3.0 This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 3.x Specification November 10, 2010
REF CLK Delayed from CLKREQ# Assertion This ECR requests making a change to the CLKREQ# asserted low to clock active timing when latency tolerance reporting is supported and enabled for the function. The change would be to allow this specified value to exceed 400ns up to a limit consistent with the latency value established by the Latency Tolerance Reporting (LTR) mechanism. 1.x ECN June 30, 2010
Protocol Multiplexing This involves a minor upward compatible change in Chapter 3, Chapter 4 and a new Appendix T. 3.x ECN June 17, 2010
End-End TLP Prefix Changes for RCs  This change allows for all Root Ports with the End-End TLP Prefix Supported bit Set to have different values for the Max End-End TLP Prefixes field in the Device Capabilities 2 register. It also changes and clarifies error handling for a Root Port receiving a TLP with more End-End TLP Prefixes than it supports. 3.x ECN May 26, 2010
Second Wireless Disable Pin This ECN is for the functional addition of a second wireless disable signal (W_DISABLE2#) as a new definition of Pin 51 (Reserved). When this optional second wireless disable signal is not implemented by the system, the original intent of a single wireless disable signal disabling all radios on the add-in card when asserted is still required. 1.x ECN May 10, 2010
Single Root I/O Virtualization and Sharing Specification Revision 1.1 with Change Bar The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology. 1.x Specification January 20, 2010
Single Root I/O Virtualization and Sharing Specification Revision 1.1 The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology. 1.x Specification January 20, 2010
CEM Support Power  ECR covers proposed modification of Section 4.2 Power Consumption within the CEM Specification version 2.0. 2.x ECN September 8, 2009
ASPM Optionality Prior to this ECN, all PCIe external Links were required to support ASPM L0s. This ECN changes the Base Specification to permit ASPM L0s support to be optional unless the applicable formfactor specification explicitly requires it. 2.x ECN August 20, 2009
Optimized Buffer Flush/Fill This ECR proposes to add a new mechanism for platform central resource (RC) power state information to be communicated to Devices. This mechanism enables Optimized Buffer Flush/Fill (OBFF) by allowing the platform to indicate optimal windows for device bus mastering & interrupt activity. Devices can use internal buffering to shape traffic to fit into these optimal windows, reducing platform power impact. 2.x ECN April 30, 2009
PCI Express Base Specification Revision 2.1 This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 2.x Specification March 4, 2009
PCI Express Base Specification Revision 2.1 with Change Bar This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 2.x Specification March 4, 2009
Errata for the PCI Express Base Specification Revision 2.0 2.x Errata February 27, 2009
Address Translation Services Revision 1.1 This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs. 1.x Specification January 26, 2009
TLP Prefix Emerging usage model trends indicate a requirement for increase in header size fields to provide additional information than what can be accommodated in currently defined TLP header sizes. The TLP Prefix mechanism extends the header size by adding DWORDS to the front of headers that carry additional information. 2.x ECN December 15, 2008
System Board Eye Height Specification Update This ECN modifies the system board transmitter path requirements (VTXS and VTXS_d) at 5 GT/s. As a consequence the minimum requirements for the add-in card receiver path sensitivity at 5 GT/s are also updated. 2.x ECN December 5, 2008
TLP Processing Hints This optional normative ECR defines a mechanism by which a Requester can provide hints on a per transaction basis to facilitate optimized processing of transactions that target Memory Space. The architected mechanisms may be used to enable association of system processing resources (e.g. caches) with the processing of Requests from specific Functions or enable optimized system specific (e.g. system interconnect and Memory) processing of Requests. 2.x ECN September 11, 2008
Extended Tag Enable Default The change allows a Function to use Extended Tag fields (256 unique tag values) by default; this is done by allowing the Extended Tag Enable control field to be set by default. 2.x ECN September 5, 2008
PCI Express Architecture Configuration Space Test Specification Revision 2.0 This document primarily covers PCI Express testing of root complexes, switches, bridges, and endpoints for the standard configuration mechanisms, registers, and features in Chapter 7 of the PCI Express Base Specification, Revision 2.0. This specification does not describe the full set of PCI Express tests and assertions for these devices. 2.x Specification August 25, 2008
Latency Tolerance Reporting This ECR proposes to add a new mechanism for Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex such that central platform resources (such as main memory, RC internal interconnects, snoop resources, and other resources associated with the RC) can be power managed without impacting Endpoint functionality and performance. 2.x ECN August 14, 2008
PCI Express Architecture Transaction Layer Test Specification Revision 2.0 This document contains a list of Test Assertions and a set of Test Definitions pertaining to the Transaction Layer. Assertions are statements of spec requirements which are measured by the algorithm details as specified in the Test Definitions. “Basic Functional Tests” are Test Algorithms which perform basic tests for key elements of Transaction Layer device functionality. This document does not describe a full set of PCI Express tests and assertions and is in no way intended to measure products for full design validation. Tests described here should be viewed as tools to checkpoint the result of product validation – not as a replacement for that effort. 2.x Specification August 11, 2008
ID-Based Ordering This ECN proposes to add a new ordering attribute which devices may optionally support to provide enhanced performance for certain types of workloads and traffic patterns. The new ordering attribute relaxes ordering requirements between unrelated traffic by comparing the Requester/Completer IDs of the associated TLPs. 2.x ECN May 29, 2008
Dynamic Power Allocation DPA (Dynamic Power Allocation) extends existing PCIe device power management to provide active (D0) device power management substates for appropriate devices, while comprehending existing PCIe PM Capabilities including PCI-PM and Power Budgeting. 2.x ECN May 24, 2008
Multi-Root I/O Virtualization and Sharing Specification Revision 1.0 The purpose of this document is to specify PCI® I/O virtualization and sharing technology. The specification is focused on multi-root topologies; e.g., a server blade enclosure that uses a PCI Express® Switch-based topology to connect server blades to PCI Express Devices or PCI Express to-PCI Bridges and enable the leaf Devices to be serially or simultaneously shared by one or more System Images (SI). Unlike the Single Root IOV environment, independent SI may execute on disparate processing components such as independent server blades. 1.x Specification May 12, 2008
Multicast This optional normative ECN adds Multicast functionality to PCI Express by means of an Extended Capability structure for applicable Functions in Root Complexes, Switches, and components with Endpoints. The Capability structure defines how Multicast TLPs are identified and routed. It also provides means for checking and enforcing send permission with Function-level granularity. The ECN identifies Multicast errors and adds an MC Blocked TLP error to AER for reporting those errors. 2.x ECN May 8, 2008
Internal Error Reporting PCI Express (PCIe) defines error signaling and logging mechanisms for errors that occur on a PCIe interface and for errors that occur on behalf of transactions initiated on PCIe. It does not define error signaling and logging mechanisms for errors that occur within a component or are unrelated to a particular PCIe transaction. 2.x ECN April 24, 2008
Resizable BAR Capability This optional ECN adds a capability for Functions with BARs to report various options for sizes of their memory mapped resources that will operate properly. Also added is an ability for software to program the size to configure the BAR to. 2.x ECN April 24, 2008
Atomic Operations This optional normative ECN defines 3 new PCIe transactions, each of which carries out a specific Atomic Operation (“AtomicOp”) on a target location in Memory Space. The 3 AtomicOps are FetchAdd (Fetch and Add), Swap (Unconditional Swap), and CAS (Compare and Swap). FetchAdd and Swap support operand sizes of 32 and 64 bits. CAS supports operand sizes of 32, 64, and 128 bits. 2.x ECN April 17, 2008
PCI Express® 225 W/300 W High Power Card Electromechanical Specification Revision 1.0 The main objective of this specification is to support PCI Express® add-in cards that require higher power than specified in the PCI Express Card Electromechanical Specification and the PCI Express x16 Graphics 150W-ATX Specification. 1.x Specification March 27, 2008
Address Translation Services 1.0 Specification Errata 1.x Errata November 30, 2007
PCI Express Mini Card Electromechanical Specification Revision 1.2 This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. 1.x Specification October 26, 2007
PCI Express Mini Card Electromechanical Specification Revision 1.2 with Change Bar This specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified sub-set of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 1.1. Where this specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. 1.x Specification October 26, 2007
Single Root I/O Virtualization and Sharing Specification Revision 1.0 The purpose of this document is to specify PCI™ I/O virtualization and sharing technology. The specification is focused on single root topologies; e.g., a single computer that supports virtualization technology. 1.x Specification September 11, 2007
Alternative Routing-ID Interpretation (ARI) For virtualized and non-virtualized environments, a number of PCI-SIG member companies have requested that the current constraints on number of Functions allowed per multi-Function Device be increased to accommodate the needs of next generation I/O implementations. This ECR specifies a new method to interpret the Device Number and Function Number fields within Routing IDs, Requester IDs, and Completer IDs, thereby increasing the number of Functions that can be supported by a single Device. 2.x ECN June 4, 2007
PCI Express Card Electromechanical Specification Revision 2.0 with Change Bar This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications. 2.x Specification April 11, 2007
PCI Express Card Electromechanical Specification Revision 2.0 This specification is a companion for the PCI Express Base Specification, Revision 2.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express® Mini Card are covered in other separate specifications. 2.x Specification April 11, 2007
Address Translation Services Revision 1.0 This specification describes the extensions required to allow PCI Express Devices to interact with an address translation agent (TA) in or above a Root Complex (RC) to enable translations of DMA addresses to be cached in the Device. The purpose of having an Address Translation Cache (ATC) in a Device is to minimize latency and to provide a scalable distributed caching solution that will improve I/O performance while alleviating TA resource pressure. This specification must be used in conjunction with the PCI Express Base Specification, Revision 1.1, and associated ECNs. 1.x Specification March 8, 2007
Errata for the PCI Express Base Specification Revision 1.1 1.x Errata February 8, 2007
PCI Express External Cabling Specification Revision 1.0 This is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of cabled PCI Express®. The discussions are confined to copper cabling and their connector requirements to meet the PCI Express signaling needs at 2.5 GT/s. No assumptions are made regarding the implementation of PCI Express compliant Subsystems on either side of the cabled Link; e.g., PCI Express Card Electromechanical (CEM), ExpressCard™, ExpressModule™, PXI Express™, system board, or any other form factor. Such form factors are covered in other separate specifications. 1.x Specification January 4, 2007
PCI Express Base Specification Revision 2.0 This specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. 2.x Specification December 20, 2006
PCI Express Card Electromechanical Specification Revision 1.1 This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications. 1.x Specification March 28, 2005
PCI Express Card Electromechanical Specification Revision 1.1 with Change Bar This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors. Other form factors, such as PCI Express Mini Card are covered in other separate specifications. 1.x Specification March 28, 2005
PCI Express Base Specification Revision 1.1 This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification. 1.x Specification March 8, 2005
PCI Express Base Specification Revision 1.1 with Change Bar This specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express specification. 1.x Specification March 8, 2005
PCI Express ExpressModule Electromechanical Specification Revision 1.0 This document is a companion specification to the PCI Express Base Specification. Its primary focus is the implementation of a modular I/O form factor that is focused on the needs of workstations and servers from mechanicals and electrical requirements. The discussions are confined to the modules and their chassis slots requirements. Other form factors are covered in other separate specifications. 1.x Specification February 14, 2005
PCI Express x16 Graphics 150W-ATX Specification Revision 1.0 The objectives of this specification are Support for PCI Express™ graphics add-in cards that are higher power than specified in the PCI Express Card Electromechanical Specification, Forward looking for future scalability, Allow evolution of the PC architecture including graphics, Upgradeability, and Enhanced end user experience. 1.x Specification October 25, 2004
PCI Express Architecture Mobile Graphics Low-Power Addendum to the PCI Express Base Specification Revision 1.0 This addendum to the PCI Express Base 1.0a describes a low power extension intended primarily to support the reduced power requirements of mobile platforms. Its scope is restricted to the electrical layer and corresponds to Section 4.3 of PCI Express Base 1.0a. 1.x Specification October 21, 2003
PCI Express to PCI/PCI-X Bridge Specification Revision 1.0 This specification describes the PCI Express to PCI/PCI-X bridge (also referred to herein as PCI Express bridge) architecture, interface requirements, and the programming model. 1.x Specification July 14, 2003
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